ADP7104ARDZ-5.0-R7 is a high-performance, low-noise, 200 mA, CMOS low-dropout (LDO) linear regulator designed and manufactured by Analog Devices Inc. (ADI). It belongs to the precision ADP710x family, engineered for powering noise-sensitive analog and RF circuitry — such as high-speed ADCs/DACs, precision op-amps, VCOs, PLLs, and RF transceivers — where ultra-low output noise, high power supply rejection ratio (PSRR), fast transient response, and stability with small ceramic capacitors are critical.
The “ARDZ” suffix denotes the 8-lead SOIC package (150 mil width) — a widely adopted, thermally robust, and manufacturable package with exposed thermal pad; the “-5.0” indicates a fixed 5.0 V output voltage; and the “-R7” signifies 7-inch tape-and-reel packaging (1,000 units per reel), Pb-free, RoHS-compliant, and qualified for industrial operation (–40°C to +125°C junction temperature).
â ī¸ Critical Clarification:
The ADP7104 is not a general-purpose LDO. It is a precision, low-noise, high-PSRR regulator optimized for signal integrity, delivering:
- 9 µVRMS output noise (10 Hz–100 kHz) — among the lowest in its class, essential for >16-bit data converters;
- 70 dB PSRR at 1 MHz, 40 dB at 10 MHz, outperforming most competing regulators in the high-frequency range where switcher ripple and digital noise dominate;
- Stability with only 1 µF ceramic output capacitance, eliminating need for large, unreliable tantalum or aluminum electrolytics;
- No external components required for basic operation — unlike many LDOs, it needs no bias capacitor or feedforward capacitor.
It operates from an input range of 3.3 V to 20 V, making it ideal for post-regulation of switching supplies (e.g., 12 V → 5 V) or direct regulation from wall adapters and industrial rails.
Introduction
The ADP7104ARDZ-5.0-R7 delivers exceptional analog performance in a standard SOIC-8 footprint:
đš Ultra-low noise: 9 µVRMS (10 Hz–100 kHz) — over 2× quieter than the LT1964 (20 µVRMS) and comparable to much higher-cost references — enabling maximum SNR in high-resolution systems;
đš High PSRR across wide bandwidth: 70 dB @ 1 MHz, 40 dB @ 10 MHz, with excellent line/load regulation (< 0.1%);
đš Fast transient response: settles within ±1% in < 5 µs for a 100 mA load step, preserving signal fidelity during dynamic digital activity;
đš Low dropout voltage: 200 mV (typ.) @ 200 mA, enabling efficient operation even with tight input–output margins (e.g., 5.2 V → 5.0 V);
đš Integrated protection: current limiting, thermal shutdown with hysteresis, and reverse-current protection — no external diodes needed.
Its SOIC-8 (ARDZ) package, with exposed thermal pad, achieves θJA ≈ 45°C/W — supporting full 200 mA load at +70°C ambient when properly heatsinked (e.g., ≥ 100 mm² EP copper area with ≥ 8 thermal vias). The device requires only two external components for basic operation: input and output ceramic capacitors.
Key Features
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High Current & Low Dropout:
• Output current: up to 200 mA;
• Dropout voltage: 200 mV (typ.) @ 200 mA, 350 mV (max);
• Input voltage range: 3.3 V to 20 V.
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Ultra-Low Noise & High PSRR:
• Output noise: 9 µVRMS (10 Hz–100 kHz) — best-in-class for 5 V LDOs;
• PSRR: 70 dB @ 1 MHz, 40 dB @ 10 MHz, 75 dB @ 120 Hz;
• Line regulation: 0.01%/V, Load regulation: 0.05% (0–200 mA).
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Fast Transient Response & Stability:
• Load transient recovery: < 5 µs to ±1% for 100 mA step (with 10 µF ceramic output cap);
• Stable with ≥ 1 µF ceramic output capacitors — no minimum ESR required;
• No external compensation needed.
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Robust Protection & Operation:
• Reverse-current protection: prevents backfeed from output to input;
• Thermal shutdown with 15°C hysteresis;
• Foldback current limiting — prevents overheating during short-circuit events;
• Enable pin (active-high) with precise 1.2 V threshold and hysteresis.
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Fixed 5.0 V Output & SOIC-8 (ARDZ) Package:
• Output voltage: 5.0 V (±1% initial accuracy, ±1.5% over line/load/temp);
• Package: 8-lead SOIC (150 mil) with exposed thermal pad (ARDZ) — excellent manufacturability and thermal performance;
• RoHS-compliant, Pb-free, and qualified for –40°C to +125°C junction temperature.
Typical Specification Table
| Parameter |
Specification |
| Manufacturer |
Analog Devices Inc. (ADI) |
| Product Series |
ADP710x Family (Low-Noise, High-PSRR LDOs) |
| Model |
ADP7104ARDZ-5.0-R7 |
| Function |
Fixed-Output Low-Dropout Linear Regulator |
| Output Voltage |
5.0 V (fixed), ±1% initial, ±1.5% over conditions |
| Max Output Current |
200 mA |
| Input Voltage Range |
3.3 V to 20 V |
| Dropout Voltage (200 mA) |
200 mV (typ.), 350 mV (max) |
| Output Noise (10 Hz–100 kHz) |
9 µVRMS |
| PSRR @ 1 MHz |
70 dB |
| Load Transient Recovery |
< 5 µs (±1%, 100 mA step, 10 µF out) |
| Min Output Capacitance |
1 µF ceramic (X5R/X7R) |
| Enable Threshold |
1.2 V (typ.), with hysteresis |
| Operating Junction Temp. |
–40°C to +125°C |
| Package |
8-Lead SOIC (150 mil) with Exposed Pad (ARDZ) |
| RoHS / Green |
Yes (Pb-free, Halogen-free) |
| Packaging |
7-inch Reel, 1,000 units (R7) |
Typical Applications
đš High-Speed Data Acquisition Systems: Powering 16–20-bit SAR and Σ-Δ ADCs (e.g., AD7960, ADS127L01) and high-fidelity DACs (e.g., AD5791, LTC2000) — where sub-10 µV RMS noise ensures maximum SNR and SFDR.
đš RF & Microwave Signal Chains: Supplying VCOs, PLLs (e.g., ADF4377), LNAs, mixers, and RF transceivers (e.g., AD9371, TRF3720) — leveraging >70 dB PSRR at 1 MHz to suppress switching regulator artifacts and preserve phase noise performance.
đš Precision Instrumentation: Powering low-noise op-amps (e.g., LT1028, ADA4898), reference buffers (e.g., ADR45xx), and strain-gauge amplifiers — where LDO noise directly limits system resolution.
đš Medical Imaging Electronics: CT/MRI detector front-ends, ultrasound beamformers, and PET scanner ASICs — requiring clean, stable 5 V rails for analog signal integrity and low artifact generation.
đš Industrial Process Control: High-accuracy sensor transmitters (e.g., 4–20 mA loop-powered sensors), precision RTD/thermocouple conditioners — benefiting from fast transient response and wide VIN tolerance.
đš Communications Infrastructure: Small cell base stations, optical modules (QSFP-DD, OSFP), and packet-processing SoCs — where low noise and high PSRR prevent BER degradation and clock jitter.
Development & Design Notes
đ§ Thermal Management:
- The ARDZ package’s exposed pad (EP) must be soldered to a ≥ 100 mm² internal ground plane using ≥ 8 thermal vias (0.3 mm) — essential for dissipating up to 1.0 W (at 12 V → 5 V @ 200 mA) without exceeding TJ = 125°C.
- For continuous 200 mA operation above +60°C ambient, add a small external heatsink or use forced airflow (>100 LFM).
đ§ Output Capacitor Selection & Layout:
- Use low-ESR, X5R or X7R ceramic capacitors (e.g., 10 µF × 2 in parallel, 0805 or 1206 size). Avoid high-ESR types (tantalum, aluminum) — they degrade PSRR and transient response.
- Place output capacitors within 3 mm of VOUT and GND pins, with short, wide traces — minimizes inductance and preserves high-frequency PSRR.
- Add a 10 nF ceramic capacitor in parallel with the main output cap, placed closest to the IC — improves high-frequency bypassing (1–10 MHz).
đ§ Input Decoupling & Ripple Rejection:
- Use a 10 µF ceramic + 1 µF ceramic at the input — located < 5 mm from IN and GND pins. This reduces high-frequency noise coupling into the LDO control loop.
- For best PSRR, ensure the input supply itself has low impedance up to 10 MHz — consider adding a ferrite bead + 100 nF cap between upstream switcher and ADP7104 if PSRR margin is tight.
đ§ Enable & Sequencing Integration:
- Tie EN to a supervisor IC (e.g., LTC2906) or microcontroller GPIO. Add a 10 nF capacitor from EN to GND for noise immunity.
- Use the enable function for power sequencing (e.g., delay 5 V rail until 3.3 V is stable) — avoids latch-up or undefined states in downstream logic.
đ§ Reliability & Long-Term Stability:
- ADP7104 exhibits < 0.3% output voltage drift over 10 years (per ADI reliability reports) — suitable for calibration-critical applications.
- For functional safety (IEC 61508 SIL-2), combine thermal monitoring (via external NTC on EP copper) with watchdog-timed readback of output voltage via optional external ADC — ADI provides FIT rate (16) and FMEDA data.
